library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity led4 is port(clk3:in std_logic; m:out std_logic_vector (3 downto 0)); end entity; architecture art of led4 is signal clk1,clk2:std_logic; begin p1:process(clk3) --分频 5Hz,系统晶振为 50MHz variable con:integer range 0 to 9999999; begin if clk3'event and clk3='1' then if con<=4999999 then clk1<='0'; con:=con